In order to manufacture a semiconductor device, various processes such as a film forming process, an etching process, an oxidation process, a diffusion process, an annealing process, a quality modification process and the like are performed on a semiconductor wafer, which is a substrate to be processed. In these processes, it is required to improve a throughput and a production yield, along with microminiaturization and high-integration of a semiconductor device. In view of the above, there is known a so-called multi-chamber type (cluster tool type) semiconductor processing equipment capable of performing various processes successively without exposing a wafer to the atmosphere by combining a plurality of process chambers for performing same or different type processes via a common transfer chamber. Such type of semiconductor processing equipment is disclosed in, e.g., Japanese Patent Laid-open Application No. 2000-127069 (see FIG. 1 thereof), and the like.
FIG. 12 is a schematic plan view of a conventional multi-chamber type semiconductor processing equipment. As shown in FIG. 12, the processing equipment has an atmospheric transfer chamber 10 arranged in parallel with a cassette stage 1. Further, a multi-joint transfer arm device 11 capable of extending, retracting and turning is provided in the atmospheric transfer chamber 10. A hexagonal vacuum transfer chamber 14 is connected with the atmospheric transfer chamber 10 via two load-lock chambers 12. A multi-joint transfer arm device 13 capable of extending, retracting and turning is disposed in the transfer chamber 14. Four vacuum process chambers 15 (for performing a film forming process or an etching process, for example) are connected with the transfer chamber 14. Furthermore, the process chambers 15 are connected with each other via gate valves 16.
In order to perform the processing, a rack-type cassette container 20 accommodating therein, e.g., 25 sheets of wafers W, is mounted on the cassette stage 1. Next, one of the wafers W is transferred from the cassette container 20 to one of the load-lock chambers 12 by the transfer arm device 11. Then, the wafer W is transferred from the load-lock chamber 12 to the transfer chamber 14 by the transfer arm device 13. Thereafter, the wafer W is loaded into an empty process chamber 15 and then subjected to, e.g., an etching process. In case the wafer W is loaded into the process chamber 15, first of all, the wafer W is delivered from the transfer arm device 13 onto three lifter pins (not shown) which will be lowered so that the wafer will be mounted on a mounting table 15a. 
After setting an imaginary reference surface in the entire apparatus, it is checked whether or not a transfer surface of the wafer W supported by the transfer arm device 13, i.e., a backside of the wafer W, is aligned with respect to the imaginary reference surface. In order to accurately exchange the wafer W, the transfer surface needs to be within ±0.3 mm from the imaginary reference surface throughout the entire access area. Such accuracy is needed because, in recent times, each of the transfer ports of the gate valves 16 is formed to have a narrow width, for improving plasma uniformity by improving symmetry in the process chambers and also for scaling down opening/closing units of the gate valves 16. Further, if the backside of the wafer W is tilted with respect to the imaginary reference surface, when the wafer W is delivered onto the lifter pins, the three lifter pins are not simultaneously contacted with the backside of the wafer W, thereby resulting in an unstable exchange of the wafer W.